// -----------------------------------------------------------------------------
// Copyright (c) 2014-2023 All rights reserved
// *********************************************************************************
// Project Name : Edge_Detect
// Author       : DFY
// File Name    : Edge_Detect.v
// Abstract     : 
module Edge_Detect(
	input clk,
	input rst_n,
	input In,
	
	output P_Pluse	
	);

reg In_1;
reg In_2;

always@(posedge clk or negedge rst_n)
	begin
		if(!rst_n)begin
			 In_1 <= 1'b0;
			 In_2 <= 1'b0;
		end
		else begin
			In_1 <= In;
			In_2 <= In_1;
		end	
	end

assign P_Pluse = (!In_2)&In_1;


endmodule